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A heterogeneous multi-pipeline architecture to enable high-performance application-specific instruction-set processor (ASIP) design is proposed. Each pipeline in this architecture is extensively customised. The program instruction-level parallelism is statically explored during compilation. Techniques such as forwarding network reduction, instruction encoding customisation and pipeline structure/instruction-set tailoring are all used to achieve a high performance/area ratio, low power consumption and small code size. The simulations and experiments on a group of benchmarks show that when the multi-pipeline ASIP is employed, an average of 83% performance improvement can be achieved when compared with a single pipeline ASIP, with overheads of 31%, 33% and 86% for area, leakage power and code size, respectively.