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A temperature reduction technique at the gate level that reduces the peak temperature through thermal-aware logic replication is presented. The technique identifies the hottest part of a given gate-netlist, extracts this from the netlist and replicates it in order to migrate the computation from one unit to the copied one whenever it exceeds a given maximum threshold temperature. The resulting gate netlist is then replaced using a thermal-aware floorplanner in order to maximise temperature reduction gain. To allow the migration from one unit to the other without any timing penalty, multiplexors and de-multiplexors between both units are inserted as well as a simple control unit with a thermal sensor on each replicated unit. Our technique ensures that only those parts of the circuit that have a high power density are replicated, and provides an autonomous hardware thermal-controlling mechanism that self-regulates itself and allows the context to swap to any replicated unit without any timing penalty. An entire temperature reduction framework is built on the top of this technique that incorporates a thermal simulator, thermal-aware floorplanner, power estimators as well as a graphical interface to manage these tools. Experimental results show that the proposed technique efficiently identifies the hottest parts of a gate netlist, replicates these and inserts the de-muxes and muxes, lowering the final peak temperature by up to 20.27degC. Further, it reduces the overall leakage power by up to 35.98%.