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The computational requirements for embedded applications are increasing exponentially. This complexity, coupled with constantly evolving specifications, has forced designers to consider intrinsically flexible implementations. In this paradigm, the digital system-on-a-chip platform-based design environment for shared memory multiple instructions multiple data architectures (Disydent) is used. Disydent is based on four tools. The distributed process network is a C library for describing Kahn process network (KPN)-based applications. The ASIM0 is a multiprocessor target platform running a micro-kernel. The cycle accurate system simulator is a high-performance cycle accurate simulator, and the user-guided high-level synthesis is a synthesis tool that may be used to enhance the platform with dedicated coprocessors. The main steps of the design flow are KPN modelling, functional validation, design space exploration and temporal validation. The applicability of the Disydent design flow to systems in the multimedia domain is illustrated. The case studied consists in deploying a motion JPEG decoder onto a configurable prototype of a multiprocessor MIPS platform. This study explores both the modelling and mapping stages of the Disydent design flow for an optimal implementation verifying constraints. For this case, the functional constraint consists in achieving a 25 frame-per-second (fps) decoding rate using 50 MHz processors as a non-functional constraint. The sequential decoder implementation does not meet the constraints. To speed up the decoding, different parallel implementations are performed on several target platforms. For more design space exploration, the influence of different scheduling policies, memory cache size and software/hardware mapping are considered.
Date of Publication: January 2009