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Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

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5 Author(s)
Sho Shimizu ; Keio University, 7-1 Shinkawasaki Saiwai-ku, Kawasaki, Japan ; Taku Kihara ; Yutaka Arakawa ; Naoaki Yamanaka
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A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

Published in:

2008 34th European Conference on Optical Communication

Date of Conference:

21-25 Sept. 2008