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Generic Low Latency Router Design for DSP Implementation on Networks-on-Chip

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3 Author(s)
Baganne, A. ; LESTER Lab., UBS Univ., Lorient, France ; Ben-Tekaya, R. ; Tourki, R.

The design of efficient router represents a key issue for the success of the network-on-chip approach. This paper presents and evaluates novel router architecture suitable for networks-on-chip (NoC) design. This router offers lowest latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using fast parallel routing (FPR) arbitration that consists in parallel processing in one stage, routing decisions and arbitration. The proposed router architecture is evaluated in 2D mesh with two adaptive routing algorithms: fully adaptive (FA) and contention look-ahead (CLA). The obtained results show that our router, combined with adaptive routing techniques is effective in terms of latency and throughput.

Published in:

Signal Processing and Communications, 2007. ICSPC 2007. IEEE International Conference on

Date of Conference:

24-27 Nov. 2007