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Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy

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2 Author(s)
Viswanathan Subramanian ; Dependable Comput. & Networking Lab., Iowa State Univ., Ames, IA, USA ; Arun K. Somani

Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree of fault tolerance and enhances performance. We replicate both the pipeline registers and the pipeline stage combinational logic. The replicated logic receives its inputs from the primary pipeline registers while writing its output to the replicated pipeline registers. The organization of redundancy in the proposed conjoined pipeline system supports overclocking, provides concurrent error detection and recovery capability for soft errors, intermittent faults and timing errors, and flags permanent silicon defects. The fast recovery process requires no checkpointing and takes three cycles. Back annotated post-layout gate level timing simulations, using 45 nm technology, of a conjoined two stage arithmetic pipeline and a conjoined five stage DLX pipeline processor, with forwarding logic, show that our approach achieves near 100% fault coverage, under a severe fault injection campaign, while enhancing performance, on an average by about 20%, when dynamically overclocked and 35%, when maximally overclocked.

Published in:

Dependable Computing, 2008. PRDC '08. 14th IEEE Pacific Rim International Symposium on

Date of Conference:

15-17 Dec. 2008