Recognizing nonseries-parallel structures in multilevel logic minimization

Traditional multilevel logic synthesis generally involves decomposing a given two-level sum-of-products expression into a series parallel network by factorization. There is a potential for greater savings if we can identify a nonseries-parallel network realizing the same function. Little work has been done in the area of recognition of nonseries-parallel structures. This paper introduces a new algorithm to identify these structures. Such structures, when present, lead to a significant reduction in literal count in the implementation of the corresponding logic functions