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Recognizing nonseries-parallel structures in multilevel logic minimization

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2 Author(s)
Jaekel, A. ; Sch. of Comput. Sci., Windsor Univ., Ont., Canada ; Bandyopadhyay, S.

Traditional multilevel logic synthesis generally involves decomposing a given two-level sum-of-products expression into a series parallel network by factorization. There is a potential for greater savings if we can identify a nonseries-parallel network realizing the same function. Little work has been done in the area of recognition of nonseries-parallel structures. This paper introduces a new algorithm to identify these structures. Such structures, when present, lead to a significant reduction in literal count in the implementation of the corresponding logic functions

Published in:

Computers and Communications, 1995., Conference Proceedings of the 1995 IEEE Fourteenth Annual International Phoenix Conference on

Date of Conference:

28-31 Mar 1995