System Level Design Methodology for Hybrid Multi-Processor SoC on FPGA

In this paper, we present a reconfigurable system on chip design framework that generates an architectural design along with binding and scheduling algorithm, specific to the input application in Kahn Process Network specification.The likelihood that tasks and communication channels may have many potential physical manifestations is explicitly recognised and embraced, to assist the design exploration process. The architectural design, binding and scheduling problems are formulated as a Integer Linear Programming problem, with physical constraints such as available logic resources, computation time and memory footprints to guide the design space exploration.