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Parallel Architecture Implementation of a Reliable (k,n) Image Sharing Scheme

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4 Author(s)
Esposito, R. ; Dept. of Electr. & Comput. Eng., Temple Univ., Temple, TX, USA ; Mountney, J. ; Li Bai ; Silage, D.

This paper presents a hardware implementation of a secure and reliable k-out-of-n threshold based secret image sharing method. The secret image is divided into n image shares so that any k image shares are sufficient to reconstruct the secret image in a lossless manner, but (k-1) or fewer image shares cannot reveal anything about the secret image. This secret sharing method comprises multiple independent computations which are conducive to parallel processing architectures. Fine-grained field programmable gate array (FPGA) architectures are the near optimal hardware platform for performing parallel processing. This paper illustrates the design and implementation of the secret image sharing method for 8-bit grayscale images on an FPGA which enhances execution time. On average, it was found that the FPGA executes image sharing and reconstruction approximately 300 times faster than a microprocessor operating on the same image.

Published in:

Parallel and Distributed Systems, 2008. ICPADS '08. 14th IEEE International Conference on

Date of Conference:

8-10 Dec. 2008