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This work presents 3-D mixed-mode simulation results of single event transients (SET) in SiGe HBT emitter followers. The impact of circuit design parameters, including biasing current and resistance are detailed. A simple increase of biasing emitter current is shown to be ineffective for hardening. Instead, during SET, the emitter voltage upset simply follows the base voltage upset due to the inherent nature of the emitter follower topology during circuit operation. The duration and the peak value of the base voltage upset are determined by the impedance and electric field between collector and base. As a result, the use of a smaller base biasing resistance is desirable for reducing SETs in emitter followers.