Referenced Items are not available for this document.
This paper describes the design process from algorithm design to the chip level for a parallel implementation of a modified version of the RSA encryption method. The final system consists of several dozens of custom chips computing module exponentiation based on residue number system coding. Emphasis is put on the hierarchical design view, its benefits and ifs shortcomings
Published in:
Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
(Volume:2
)
Date of Conference: 19-21 Apr 1995
- Page(s):
- 849 - 854 vol.2
- Meeting Date :
- 19 Apr 1995-21 Apr 1995
- Print ISBN:
- 0-7803-2018-2
- INSPEC Accession Number:
- 5065493
- Conference Location :
- Brisbane, Qld.
- Digital Object Identifier :
- 10.1109/ICAPP.1995.472276
- Product Type:
- Conference Publications
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