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Instruction Set Extensions for Enhancing the Performance of Symmetric-Key Cryptography

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2 Author(s)

Instruction set extensions for a RISC processor are presented to improve the software performance of the Data Encryption Standard (DES), Triple-DES, the International Data Encryption Algorithm (IDEA), and the Advanced Encryption Standard (AES) algorithms. The most computationally intensive operations of each algorithm are off-loaded to a set of newly defined instructions. The additional hardware required to support these instructions is integrated into the processor's datapath. For each of the targeted algorithms, comparisons are presented between traditional software implementations and new implementations that take advantage of the extended instruction set architecture. Results show that utilization of the proposed instructions significantly reduces program code size and improves encryption and decryption throughput. Moreover, the additional hardware resources required to support the instruction set extensions increases the total area of the processor by less than 65%.

Published in:

Computer Security Applications Conference, 2008. ACSAC 2008. Annual

Date of Conference:

8-12 Dec. 2008