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Reconfigurable gate array architectures for real time digital signal processing

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2 Author(s)
Liersch, G. ; Dept. of Electron. Eng., La Trobe Univ., Bundoora, Vic., Australia ; Dick, C.

The number of usable gates in field programmable gate array (FPGA) logic has recently reached a level which allows their use as computational structures in digital signal processing (DSP) applications. This paper reports on the development of a scalable computing architecture based on Xilinx (CMOS) XC4010 FPGAs for real-time digital signal processing. The architecture requirements for efficient implementation of common DSP algorithms on FPGA platforms are considered. An analysis of the implementation and performance of a high-bandwidth finite impulse response (FIR) filter is presented. A second design using data requantization and spectral shaping to achieve higher order filters is also described

Published in:

Signals, Systems and Computers, 1994. 1994 Conference Record of the Twenty-Eighth Asilomar Conference on  (Volume:2 )

Date of Conference:

31 Oct-2 Nov 1994