By Topic

An integrated ASIP design flow for digital signal processing applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Vladimir Guzma ; Department of Computer Systems, Tampere University of Technology, FI-33720, Finland ; Shuvra S. Bhattacharyya ; Pertti Kellomaki ; Jarmo Takala

Application specific instruction set processors (ASIP) allow designers to optimize the architecture of an embedded processor to meet the specific demands of a particular application. A complementary form of customization is provided by domain-specific models of computation (MoCs), which can expose the high level structure of applications that is useful for various kinds of optimizing design transformations. One such MoC is Synchronous Dataflow (SDF), which is used increasingly in the design and implementation of signal processing applications. In this paper, we develop an integration of SDF- and ASIP-oriented design flows, and use this integrated design flow to explore trade-offs in the space of hardware/software implementations. We also explore an approach to ASIP implementation in terms of ldquocriticalrdquo and ldquonon-criticalrdquo applications, which allows designers to tune the degree of specialization for a targeted ASIP. Our results show that single ASIP processor tuned for pair of critical applications saves 26% to 50% of area required for implementations of two applications on separate ASIPs and non-critical applications runs on such processor with in worst case 4.5% overhead for our selection of benchmarks.

Published in:

2008 First International Symposium on Applied Sciences on Biomedical and Communication Technologies

Date of Conference:

25-28 Oct. 2008