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This paper focuses on high level integration of analog on today's products. We will present the paradigm change required to test these circuit from ATE driven solutions to DFT/BIST/BOST techniques. We will present industrial examples of implementation and silicon results. The examples will range from PLL Testing using ATE approaches and on-chip jitter measurements (TDC based approach) to ADC testing using on chip ramp generation and off chip active TIU (Test Interface Unit) approach to PCIe testing using capable tester to DFT based methods. The talk will focus on what techniques performed well and provided a good alternative solution and which ones resulted in more yield loss or high DPM escapes.