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Since scan testing is not based on the function of the circuit, but rather its structure, scan testing is considered to be a form of over testing or under testing. It is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper proposes a test generation method to detect specified fault models completely and to increase defect coverage as much as possible under test length constraint. We give experimental results for MCNC'91 benchmark circuits to evaluate bridging fault coverage, transition fault coverage, and statistical delay quality level and show the effectiveness of the proposed test generation method compared with a stuck-at fault-dependent test generation method.