By Topic

Low-cost reconfigurable VLSI architecture for fast fourier transform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hao Xiao ; Fudan University ; An Pan ; Yun Chen ; Xiaoyang Zeng

In this paper, a low-cost reconfigurable FFT processor employing novel dual-path pipelined shared memory architecture is presented. Based on this architecture, an elaborate memory configuration scheme is designed to make single-port SRAM available. Moreover, a mixed-radix butterfly unit is also designed, which makes the processor capable of multimode operation. Compared with previous ones, the proposed architecture can greatly reduce area. In addition, an optimized data scaling approach is proposed and the signal-to-quantization noise ratio (SQNR) of an 8K-point fixed-point FFT can achieve 52.7dB with the wordlength of 13bit. A test chip for DVB-T/H is implemented with the proposed architecture and fabricated in 0.18-mum single-poly six-metal CMOS process. The core area of this chip is 2.83mm2 with the power dissipation of 25.8mW at 20MHz.

Published in:

IEEE Transactions on Consumer Electronics  (Volume:54 ,  Issue: 4 )