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High-Performance Hardware Architectures for Galois Counter Mode

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3 Author(s)
Akashi Satoh ; National Institute of Advanced Industrial Science and Technology, Tokyo ; Takeshi Sugawara ; Takafumi Aoki

Various high-performance hardware architectures for Galois counter mode (GCM) in conjunction with various advanced encryption standard (AES) circuits and multiplier-adders are proposed. A total of 17 GCM-AES circuits were synthesized by using a 130-nm CMOS standard cell library, and the trade-offs between speed and hardware resources were evaluated. Our flexible architectures achieved a wide variety of performances from compact (2.56 Gbps with 34.5 Kgates) to high speed (62.6 Gbps with 979.3 Kgates). All of our architectures support key sizes of 128, 192, and 256 bits, while only one previous approach does. Even with variable-length key support, our architecture also achieved the highest hardware efficiency (defined as throughput per gate) among the designs using the same generation of process technology.

Published in:

IEEE Transactions on Computers  (Volume:58 ,  Issue: 7 )