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On-chip digital Idn and Idp measurement by 65 nm CMOS speed monitor circuit

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5 Author(s)
Notani, H. ; Renesas Technol. Corp., Itami ; Fujii, M. ; Suzuki, H. ; Makino, H.
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An on-chip digital Ids measurement method is proposed in this report. In the proposed method, Ids is digitally derived from the two values measured by three ring oscillators with PN balanced, N-rich, and P-rich inverters. The first value is the frequency of the PN balanced inverter ring. The second value is the frequency difference between the N-rich and the P-rich inverter rings. The post-digital processing derives NMOS Ids (Idn) and PMOS Ids (Idp) separately. The monitor circuit was implemented by 65 nm CMOS technology. The mismatch error between the first Ids calculated from measured frequencies, and the second Ids directly measured for reference, was analyzed. The standard deviations of the mismatch error in Idn and Idp are 1.64% and 1.09%, respectively. The margin of 3sigma is within 5% which is our target tolerance for a practical application.

Published in:

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Date of Conference:

3-5 Nov. 2008

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