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A 20-Gb/s full-rate 27-1 PRBS generator integrated with 20-GHz PLL in 0.13-μm CMOS

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3 Author(s)
Jeong-Kyoum Kim ; Sch. of EECS & ISRC, Seoul Nat. Univ., Seoul ; Jaeha Kim ; Deog-Kyoon Jeong

This paper presents 20-Gb/s full-rate 27-1 PRBS generator with 20-GHz PLL. Implemented in a 0.13-mum CMOS process with fT of only about 80 GHz, the proposed PRBS core achieves 20-Gb/s full-rate by using pulsed latches instead of flip-flops and XOR gates with inductive peaking and negative feedback. The clock buffers that drive the 20-GHz clock distribution and the pulsed-latches in the PRBS core also employ single-transformer based inductive peaking and negative feedback to achieve bandwidth of 73 GHz. The measured data jitter of the 18.8-Gb/s PRBS output is 2.78 psrms and 14.4 pspp. The measured clock jitter of the divided-by-16 clock is 1.99 psrms and 14.4 pspp. The fabricated PRBS generator and PLL dissipate 0.84 W and 0.17 W, respectively, from a 1.5-V supply.

Published in:

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Date of Conference:

3-5 Nov. 2008