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A 65 fJ/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3D system integration

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5 Author(s)
Kiichi Niitsu ; Department of Electronics and Electrical Engineering, Keio University, Yokohama, Kanagawa, Japan ; Shusuke Kawai ; Noriyuki Miura ; Hirold Ishikuro
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This paper discusses a low-power inductive-coupling link in 90 nm CMOS. The novel transmitter circuit using charge recycling technique for power-aware three-dimensional (3D) system integration is proposed and investigated. Cross-type daisy chain enables charge recycling and achieves power reduction while keeping communication performance such as high timing margin, low bit error rate and high bandwidth. There are two design issues in cross-type daisy, one is pulse amplitude reduction and another is inter-channel skew. To compensate them, inductor design and replica circuit is proposed and investigated. Test chips were designed and fabricated in 90 nm CMOS to verify the proposed transmitter. Measured result showed that proposed cross-type daisy chain transmitter achieved an energy efficiency of 65 fJ/bit without degrading any of timing margin, data rate and bit error rate.

Published in:

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Date of Conference:

3-5 Nov. 2008