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In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.