Referenced Items are not available for this document.
A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.
Published in:
Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian
Date of Conference: 3-5 Nov. 2008
- Page(s):
- 45 - 48
- E-ISBN :
- 978-1-4244-2605-8
- Print ISBN:
- 978-1-4244-2604-1
- INSPEC Accession Number:
- 10423571
- Conference Location :
- Fukuoka
- Digital Object Identifier :
- 10.1109/ASSCC.2008.4708725
- Product Type:
- Conference Publications
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