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A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology

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2 Author(s)
Yuan-Ching Lien ; Nat. Taiwan Univ., Taipei ; Jri Lee

A 6-b 1-GS/s subranging ADC with THA is implemented in 90-nm CMOS technology. This circuit incorporates folded input for the fine ADC as well as offset calibration and digital correction techniques, achieving greater than 5.2 ENOB and 40-dB SFDR up to the Nyquist, and 1.1-GHz ERBW with power consumption of only 30 mW.

Published in:

Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian

Date of Conference:

3-5 Nov. 2008