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CMOS bridges and resistive transistor faults: IDDQ versus delay effects

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3 Author(s)
H. T. Vierhaus ; German Nat. Res. Center for Comput. Sci., Syst. Design Technol. Inst., St. Augustin, Germany ; W. Meyer ; U. Glaser

Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing

Published in:

Test Conference, 1993. Proceedings., International

Date of Conference:

17-21 Oct 1993