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A method to derive compact test sets for path delay faults in combinational circuits

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2 Author(s)
Saxena, J. ; Texas Instrum. Inc., Dallas, TX, USA ; Pradhan, D.K.

In path delay fault testing, the number of faults to be tested in a circuit is inherently very large. Therefore, deriving compact test sets for path delay faults is an important issue. This paper presents a method to derive compact test sets for path delay faults by using the notion of compatible faults. A technique to derive maximal compatible path delay fault sets is described. The technique is based on identifying necessary conditions on lines in a circuit along with values a line cannot take in order to test a given path. Experimental results on ISCAS benchmarks are presented to demonstrate the effectiveness of using this technique in reducing test set size

Published in:

Test Conference, 1993. Proceedings., International

Date of Conference:

17-21 Oct 1993

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