Referenced Items are not available for this document.
In this paper we present a new approach to the design of multilevel fault-tolerant circuits. The approach is based on introducing a minimal amount of fault-masking redundancy during a multilevel logic optimization, process. This is done by taking into account the degrees of freedom associated with internal don't care conditions. Experimental results obtained on several benchmark circuits compare very favourably with fault-tolerant implementations based on traditional gate-level strategies
Published in:
European Design and Test Conference, 1995. ED&TC 1995, Proceedings.
Date of Conference: 6-9 Mar 1995
- Page(s):
- 80 - 85
- Meeting Date :
- 06 Mar 1995-09 Mar 1995
- Print ISBN:
- 0-8186-7039-8
- INSPEC Accession Number:
- 5044352
- Conference Location :
- Paris
- Digital Object Identifier :
- 10.1109/EDTC.1995.470416
- Product Type:
- Conference Publications
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