Referenced Items are not available for this document.
We describe how a zero-order hold digital-to-analog converter (DAC) followed by a windowed-integration-based filter results in a novel partial-order hold (POH) DAC architecture with the ability of broadband image reduction between 1.5 and two times the sampling frequency while also providing a flat-group delay. Interleaving two such POH-DACs results in a DAC with an excellent output signal reconstruction whereby the broadband sampling images below two times the sampling frequency in the output signal spectrum are strongly reduced. Some implementation techniques are proposed and the effect of implementation nonidealities is evaluated.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:55
,
Issue:
11
)
Date of Publication: Nov. 2008
- Page(s):
- 1109 - 1113
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 10360149
- Digital Object Identifier :
- 10.1109/TCSII.2008.2004538
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 09 December 2008
- Issue Date :
- Nov. 2008
- Sponsored by :
- IEEE Circuits and Systems Society
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