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Bit parallel test pattern generation for path delay faults

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2 Author(s)
Henftling, M. ; Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany ; Wittman, H.

A method to apply bit-parallel processing at all stages of robust and nonrobust test pattern generation for path delay faults is presented. Two different modes of bit-parallel processing are combined: fault parallel test pattern generation (FPTPG) and alternative parallel test pattern generation (APTPG). We discuss the problems that appear while exploiting bit-parallelity and we describe how to overcome them. Experimental results demonstrate a reduction of aborted faults and an acceleration up to a factor of nine

Published in:

European Design and Test Conference, 1995. ED&TC 1995, Proceedings.

Date of Conference:

6-9 Mar 1995