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Hardware Overhead Reduction for Memory BIST

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4 Author(s)
Arai, M. ; Tokyo Metropolitan Univ., Tokyo ; Iwasaki, K. ; Nakao, M. ; Suzuki, I.

We propose encoder-based comparator architecture to reduce hardware overhead of MBIST. Experimental results show the proposed architecture drastically reduce hardware overhead while maintaining the adaptability to the repair analysis.

Published in:

Test Conference, 2008. ITC 2008. IEEE International

Date of Conference:

28-30 Oct. 2008

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