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CONCAT: CONflict Driven Learning in ATPG for Industrial designs

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4 Author(s)
Bommu, S. ; Intel Corp., Santa Clara, CA ; Chandrasekar, K. ; Kundu, R. ; Sengupta, S.

In this paper, we propose a new search technique for ATPG, called CONCAT [1], which (a) is based on AND/OR reasoning, (b) integrates conflict driven learning, and (c) avoids over specification of test vectors. The technique works seamlessly (i) between Boolean and non-Boolean gates in industrial designs, (ii) across phases in latch-based designs, (iii) between justification and propagation tasks in sequential ATPG, and (iv) across faults in the fault list. Experimental results on combinational ISCAS circuits against SAT-based ATPG, show that we can reduce the test vector specification by upto 74%, with consistent improvement in performance and capacity. We integrated the CONCAT technique into Intel's existing ATPG tool, called Aztec, and obtained upto 67% speed-up and upto 14% more ATPG effectiveness on industrial designs.

Published in:

Test Conference, 2008. ITC 2008. IEEE International

Date of Conference:

28-30 Oct. 2008

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