A Ubiquitous Processor Free from Instruction Scheduling

VLSI is a significant area of ever growing ICT. In the development of cutting edge VLSI processors, parallelism is one of the most important global standard strategies to achieve power conscious high performance. These features are more critical for ubiquitous systems with a great demand. In order to fully utilize hardware parallelism, software parallelism like TLP and ILP is also inevitable. Considering ILP for regular scalar units need awkward instruction scheduling, we explore a double scheme or the multifunctionalization and wave-pipelining of scalar units. The multifunctionalization frees the instruction scheduling. Then, wave-pipelining recovers the reduction of clock speed to be caused by the scale up of a multifunctional circuit. We describe in this article the improvement of a ubiquitous processor, HCgorilla by using the double scheme. The improved HCgorilla is promising for wide-range dynamic ILP at a rate higher than regular processors.