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A channel decoder implemented by CMOS analog circuits in digital communication system

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3 Author(s)
Shuhui Yang ; Coll. of Photoelectricity Inf. & Commun. Eng., Beijing Inf. Sci. & Technol. Univ., Beijing ; Xuehua Li ; Yafei Wang

To realize low power channel decoder in digital communication system, basing on the a-posteriori probability algorithm, the paper fabricates an analog probability decoder of trellis code by using CMOS analog circuits. The decoding performance is given. When the SNR is over 4.8 dB, for 950 KHz input signal, the analog decoderpsilas BER is zero. If the input signal is 6 MHz, the BER will be about 10-4.The highest speed of the decoder can be up to 20 MHz. Simulation results also show that the analog decoder decreases at least one order of magnitude in power consumption and chip area at the same rate compared with the digital decoder. The design method is also suitable for implementing the analog decoders of Turbo code and LDPC code.

Published in:

Signal Processing, 2008. ICSP 2008. 9th International Conference on

Date of Conference:

26-29 Oct. 2008