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There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated factors. These factors affect decoder computation and communication complexity, and error-correcting performance. In this paper we present a low-complexity, flexible and scalable LDPC decoder architecture for quasi-cyclic codes that supports multiple code designs (size, weights, rates, regular and irregular). The architecture is a result of a combination of flexible code construction and computation overlapping techniques. The architecture is based on overlapping techniques that allow sequential processing of check and variable nodes. The overlapping techniques lead to a low-complexity decoder interconnect compared to the existing techniques as they allow serial processing of code sub-matrices as compared to parallel processing of all sub-matrices in the existing overlapping technique. Although the architecture is based on quasi-cyclic codes, it can also be applied to random or other structured codes making it the most flexible, scalable and high-throughput partly-parallel LDPC decoder architecture.
Date of Conference: 26-29 Oct. 2008