By Topic

Integrated CMOS imager for pattern recognition

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Sarje, A. ; Dept. of Electr. & Comput. Eng., Univ. of Maryland, College Park, MD ; Satsangi, S. ; Skipwith, A.C. ; Chiang, J.-P.
more authors

This paper presents an analog CMOS architecture for on-chip pattern recognition. The system comprises a CMOS imager in the front end followed by low power computation circuitry for determining a match between the captured image and image patterns stored in on-chip memory. The imager has a programmable kernel selector and correlated double sampling circuit for suppression of fixed pattern noise. The closeness of a successful match can be controlled by an input bias current. The prototype with a 6 times 6 pixel array in a 0.5 mum CMOS process is being implemented. This chip can be used for applications requiring dedicated pattern recognition.

Published in:

Biomedical Circuits and Systems Conference, 2008. BioCAS 2008. IEEE

Date of Conference:

20-22 Nov. 2008