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In this paper, the author proposes a novel testing-based system-on-a-chip (SoC)/very large scale integration (VLSI) intellectual property (IP) identification and protection platform in SoC/VLSI design. The principles are established for the development of a new IP identification, protection procedures, and a digital rights management system that depends on the current IP-based design flow. This platform can successfully survive synthesis, placement, and routing and identify the IP core at various design levels. The proposed method has the potential to solve the digital rights management problem in SoC/VLSI design.