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This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design. The proposed environment allows efficient power estimation of custom reconfigurable cores through state based power modeling, leading to a viable solution for early power aware design. The simulator has been applied to SystemC module of a custom reconfigurable core for Viterbi decoding. Power figures have been compared with the results obtained by state of the art industrial tools.
Date of Conference: 5-6 Nov. 2008