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Synchronization in a Multilevel CMOS Time-to-Digital Converter

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3 Author(s)
Jussi-Pekka Jansson ; Dept. of Electr. & Inf. Eng., Univ. of Oulu, Oulu, Finland ; Antti Mantyniemi ; Juha Kostamovaara

Accurate time-to-digital conversion is typically based on determining the positions of the timing signals within the period of an accurate clock with digital delay-line interpolators. In order to save circuit area and to improve single-shot precision to the picosecond level, multilevel interpolators can be used. Timing signals are generally asynchronous with respect to the main clock, and thus, in order to obtain unambiguous and errorless results, careful attention should be given to the synchronization of the timing signals and various operating blocks and to the generation of the interpolation residue between the interpolators. This paper attempts to describe these problems in detail and suggests some solutions using a time-to-digital converter architecture based on two-level interpolation as a test vehicle, which demonstrates 6-ps rms single-shot precision in a measurement range of 1 ms.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:56 ,  Issue: 8 )