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Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

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5 Author(s)
Banna, S.R. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol, Hong Kong ; Chan, M. ; Ko, P.K. ; Nguyen, C.T.
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The threshold voltage, Vth, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the Vth roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, ΔVth is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V th design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted Vth design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained

Published in:

Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 11 )

Date of Publication:

Nov 1995

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