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CAD-compatible high-speed CMOS/SIMOX gate array using field-shield isolation

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5 Author(s)
Iwamatsu, T. ; ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan ; Yamaguchi, Y. ; Inoue, Y. ; Nishimura, T.
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A specific 0.5 μm CMOS/SIMOX technology was developed for a gate array/sea of gate (SOG) using field-shield (FS) isolation to overcome a pending problem of source-to-drain breakdown voltage (BVds) lowering. FS isolation is capable of improving BVds because surplus holes generated by impact ionization at the drain region are collected through the body region under the FS gate. BVds was maintained at a level of junction breakdown before reaching the punchthrough limitation at a gate length of around 0.3 μm using the FS isolation. The FS isolation technique was successfully applied to an SOG gate array on a SIMOX substrate. The gate array has the same area as that on the bulk-Si and is compatible to a conventional bulk-Si CAD system because the layout is basically the same. A 53-stage ring oscillator fabricated on the FS isolated SOG gate array exhibited 1.7 times higher speed operation than that on a bulk-Si counterpart, keeping low power consumption characteristics up to a drain voltage of 3 V

Published in:

Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 11 )

Date of Publication:

Nov 1995

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