Close category search window
 

Review on Spacecraft Formal System Design Verification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Huamao Wang ; China Acad. of Space Technol., Beijing ; Yan Wang

This paper introduces a system design verification method - Formal verification methods. The verification methods overcome the insufficiency of traditional test verification and simulation verification, it will omnidirectional verify the correctness of the design. By introducing formal system design and verification methods, pointing out that the formal verification ideas of the spacecraft design.

Published in:
Embedded Computing, 2008. SEC '08. Fifth IEEE International Symposium on

Date of Conference: 6-8 Oct. 2008

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.