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Optimization of the Averaging Reliability Technique Using Low Redundancy Factors for Nanoscale Technologies

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3 Author(s)
Stanisavljevic, M. ; Microelectron. Syst. Lab. (LSM), Swiss Fed. Inst. of Technol. (EPFL), Lausanne ; Schmid, A. ; Leblebici, Y.

This paper presents a method enabling the evaluation of the averaging fault-tolerant technique, using the output probability density functions of unreliable units that are acquired from Monte Carlo simulations. The method has been verified by comparing numerical simulations and analytical developments. A fault-tolerant four-layer architecture using averaging and with both fixed and adaptable threshold is compared with triple and R-fold modular redundancy (RMR) techniques, at gate level and using fault-free decision gates, showing that the redundancy factor can be reduced by a factor of two to three using the proposed four-layer architecture, in replacement of RMR, thus enabling significant savings in the area, and power dissipation. The analysis of the reliability of averaging techniques together with the redundancy optimization has been performed for the first time in the context of a large-scale system, showing that a target reliability can be achieved with low redundancy factors (R < 8) for moderate defect densities (device failure rate up to 10-5). The performed analysis of the optimal size of the reliable islands (clusters) supports the assumption that clustering needs to be applied at the lower levels of design abstraction hierarchy, especially for fabrication technologies with increased defect density.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:8 ,  Issue: 3 )

Date of Publication:

May 2009

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