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Fast Configurable-Cache Tuning With a Unified Second-Level Cache

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3 Author(s)
Gordon-Ross, A. ; Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL ; Vahid, F. ; Dutt, N.D.

Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or a second level with separate instruction and data configurable caches. We instead use a commercially-common unified second level cache, a seemingly minor difference that actually expands the configuration space from 500 to about 20 000. We develop additive way tuning for tuning a cache subsystem with this large space, yielding 61% energy savings and 9% performance improvements over a nonconfigurable cache, greatly outperforming an extension of a previous method.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 1 )

Date of Publication:

Jan. 2009

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