By Topic

Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hua Wang ; IMEC, Katholieke Univ. Leuven, Leuven ; Miranda, M. ; Dehaene, W. ; Catthoor, F.

This paper presents a formalized synthesis methodology for variable tapered buffer chains achieving Pareto optimal energy-delay (E/D) tradeoffs via the buffer gate sizes and adding supply voltage as an extra tuning knob. In addition, a detailed discussion of the practically achievable tradeoff ranges via the gate size and especially supply voltage tuning is present. We have applied the methodology for the design and fine tuning of the run-time switchable buffers within the Level-1 (L1) embedded SRAMs (eSRAM), confirming that a very wide range in delay and energy reduction (up to 50%) can be achieved when compared to solely optimal speed eSRAM design using conventional high speed buffers.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 1 )