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Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications

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4 Author(s)
Chan, J. ; Dept. of Electr. Eng., Columbia Univ., New York, NY ; Biberman, A. ; Lee, B.G. ; Bergman, K.

An on-chip photonic interconnection network is simulated to determine statistical insertion losses for different network sizes and non-blocking switch layouts. For an 8times8 folded-torus network, we obtain an optical link loss budget of 15.5 dB.

Published in:

IEEE Lasers and Electro-Optics Society, 2008. LEOS 2008. 21st Annual Meeting of the

Date of Conference:

9-13 Nov. 2008