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Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications

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4 Author(s)
Johnnie Chan ; Department of Electrical Engineering, Columbia University, New York, 10027 USA ; Aleksandr Biberman ; Benjamin G. Lee ; Keren Bergman

An on-chip photonic interconnection network is simulated to determine statistical insertion losses for different network sizes and non-blocking switch layouts. For an 8times8 folded-torus network, we obtain an optical link loss budget of 15.5 dB.

Published in:

LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society

Date of Conference:

9-13 Nov. 2008