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The application of independent component analysis (ICA) algorithm can achieve a real time blind signal separation (BSS) if it is physically implemented using hardware devices. However, due principally to both of the limited size and of the microelectronics technology of the used hardware devices, many practical problem can be encountered to reach the real time processing since the application of the ICA algorithm requires the consumption of a huge number of input signal samples. Hence, the system performance was degraded since we required the consumption of an important number of memory circuits with faster hardware execution time. Therefore, in order to improve the hardware performances of the device, in this paper, the authors proposed the sequential processing of one neuron hardware model based on field programmable gate array (FPGA) implementation. Such approach overcomes the interconnections complexities of the FPGA architecture. Thus, an optimal digital circuit design can be proposed to avoid the consumption of much hardware resources in which a maximum number of samples can be handled while maintaining high speed of hardware processing time. The proposed approach was demonstrated through the experimental study of TIMIT data base exhibiting a hardware execution time of 3.3 mus to process 10000 samples with 57 KHz of sample rates to separate two output independent signals from two input mixed signals.
Date of Conference: 16-19 Oct. 2008