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A CMOS Fingerprint System-on-a-Chip With Adaptable Pixel Networks and Column-Parallel Processors for Image Enhancement and Recognition

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4 Author(s)
Seong-Jin Kim ; Lab. of Multimedia, Samsung Adv. Inst. of Technol., Yongin ; Kwang-Hyun Lee ; Sang-Wook Han ; Euisik Yoon

We propose a 200times160 pixel CMOS fingerprint system-on-a-chip with a local adaptive pixel scheme and embedded column-parallel processors for performing 2-D digital image processing for fingerprint recognition. The pixel includes a sensing block, ADC, and in-pixel frame memory with no additional area penalty. The sensor can capture robust fingerprint images in various finger conditions using a locally adapted capacitive sensing scheme through adaptable pixel networks. The embedded parallel processors can enhance the captured image in digital signal domain by self-reconfigurable signal processing including low-pass and band-pass filtering, and create the thinned image for fingerprint recognition. A test chip has been fabricated using a 0.5 mum standard CMOS process. We have successfully captured and characterized the fingerprint images from the fabricated test chip at each step of adaptive signal processing steps. The total execution time for acquiring and processing a fingerprint image is less than 360 ms at 10 MHz and the power consumption is below 70 mW at 3.3 V supply voltage. The proposed sensor can be applied to personal identification systems for portable devices such as cellular phones, PDA and smart cards.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:43 ,  Issue: 11 )