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A sub-harmonic injection-locked tripler multiplies a 20-GHz differential input to 60-GHz quadrature (I/Q) output signals. The tripler consists of a two-stage ring oscillator driven by a single-stage polyphase input filter and 50-Omega I and Q-signal output buffers. Each gain stage incorporates a hard limiter to triple the input frequency for injection locking and a negative resistance cell with two positive feedback loops to increase gain. Regenerative peaking is also used to optimize the gain/bandwidth performance of the 50-Omega output buffers. Fabricated in 90-nm CMOS, the tripler has a free-running frequency of 60.6 GHz. From a 0-dBm RF source, the measured output lock range is 56.5-64.5 GHz, and the measured phase noise penalty is 9.2 plusmn 1 dB with respect to a 20.2-GHz input. The 0.3 times 0.3 mm2 tripler (including passives) consumes 9.6 mW, while the output buffers consume 14.2 mW, all from a 1-V supply.