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A clock multiplier combines the low reference spur of a PLL with the low phase noise of a recirculating DLL. It uses a ring oscillator that has two pulses running simultaneously that are phase independent. One pulse is used by a PLL to precisely set ring delay while the other pulse is periodically realigned with the reference phase by a process of pulse removal and reinsertion, similar to a DLL. The DLL reference spur due to static phase offset is eliminated, since the realigned pulse is not used to control the delay. A self-correcting charge pump is introduced that corrects for mismatches in the actual up-and down currents. The 0.048 mm2 90 nm CMOS circuit has -122 dBc/Hz phase noise @ 200 kHz offset of an 800 MHz carrier, - 48 dBc reference spur and consumes 15 mW from a 1 V supply.