System Maintenance:
There may be intermittent impact on performance while updates are in progress. We apologize for the inconvenience.
By Topic

Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Gierkink, S.L.J. ; Axiom IC, Enschede

A clock multiplier combines the low reference spur of a PLL with the low phase noise of a recirculating DLL. It uses a ring oscillator that has two pulses running simultaneously that are phase independent. One pulse is used by a PLL to precisely set ring delay while the other pulse is periodically realigned with the reference phase by a process of pulse removal and reinsertion, similar to a DLL. The DLL reference spur due to static phase offset is eliminated, since the realigned pulse is not used to control the delay. A self-correcting charge pump is introduced that corrects for mismatches in the actual up-and down currents. The 0.048 mm2 90 nm CMOS circuit has -122 dBc/Hz phase noise @ 200 kHz offset of an 800 MHz carrier, - 48 dBc reference spur and consumes 15 mW from a 1 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:43 ,  Issue: 12 )